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W137
FTG for Mobile 440BX & Transmeta's Crusoe CPU
Features
* Maximized EMI suppression using Cypress's Spread Spectrum Technology * Two copies of CPU output * Six copies of PCI output (Synchronous w/CPU output) * One 48-MHz output for USB support * One selectable 24 /48 MHz output * Two Buffered copies of 14.318 MHz input reference signal * Supports 100 MHz or 66 MHz CPU operation * Power management control input pins * Available in 28-pin SSOP (209 mils) and 28-pin TSSO (173 mils) * SS function can be disabled * See W40S11-02 for 2 SDRAM DIMM support CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps PCI_F, PCI1:5 Output to Output Skew:....................... 500 ps PCI_F, PCI1:5 Cycle to Cycle Jitter: .......................... 250 ps CPU to PCI Output Skew:................1.5-4.0 ns (CPU Leads) Output Duty Cycle:..................................................... 45/55% PCI_F, PCI Edge Rate: .............................................. >1 V/ns CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#, PWR_DWN# all have a 250-kW pull-up resistor. Table 1. Pin Selectable Frequency SEL100/66# 0/1 0 1 OE 0 1 1 CPU Hi-Z 66.6 MHz 100 MHz PCI Hi-Z 33.3 33.3 Spread% Don't Care See Table 2 See Table 2
Key Specifications
Supply Voltages:........................................ VDDQ3 = 3.3V5% VDDQ2 = 2.5V5% CPU0:1 Output to Output Skew: ................................. 175 ps
Table 2. Spread Spectrum Feature SPREAD# 0 1 Spread Profile -0.5% (down spread) 0% (spread disabled)
Block Diagram of the anchored frame as per requirement>
Pin Configuration
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 8
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W137
Pin Definitions
Pin Name CPU0:1 Pin No. 24, 23 Pin Type O Pin Description CPU Clock Outputs 0 and 1. These two CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. Frequency is selected per Table 1. PCI Bus Clock Outputs 1 through 5. These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. Fixed PCI Clock Output. Unlike PCI1:5 outputs, this output is not controlled by the PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. CPU_STOP# Input. When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 start with a full clock cycle (2-3 CPU clock latency). PCI_STOP# Input. The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. I/O Dual-Function REF0 and SEL48# Pin. Upon power-up, the state of SEL48# is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to VDD, pin 14 will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. I/O Dual-Function REF1 and SPREAD# Pin. Upon power-up, the state of SPREAD# is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND enables Spread Spectrum function. If the pin is strapped to VDD, Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. I/O Dual-Function 24 MHz or 48 MHz Output and Output Enable Input. Upon power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND latches OE LOW, and all outputs are tri-stated. If the pin is strapped to VDD, OE is latched HIGH and all outputs are active. After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27 on power-up. 48 MHz Output. Fixed 48 MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection Input. Select power-up default CPU clock frequency as shown in Table 1. Crystal Connection or External Reference Frequency Input. This pin can either be used as a connection to a crystal or to a reference signal. Crystal Connection. An input connection for an external 14.318 MHz crystal. If using an external reference, this pin must be left unconnected. Power Down Control. When this input is LOW, device goes into a low-power standby condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock cycle latency). When brought HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Power Connection. Connected to 3.3V. Power Connection. Power supply for CPU0:1 output buffers. Connected to 2.5V. Ground Connection. Connect all ground pins to the common system ground plane.
PCI1:5
5, 6, 9, 10, 11
O
PCI_F
4
O
CPU_STOP#
18
I
PCI_STOP#
20
I
REF0/SEL48#
27
I/O
REF1/SPREAD#
26
I/O
24/48MHz/OE
14
I/O
48MHz SEL100/66# X1 X2 PWR_DWN#
13 16 2 3 17
O I I I I
VDDQ3 VDDQ2 GND
8, 12, 19, 28 25 1, 7, 15, 21, 22
P P G
Rev 1.0, November 24, 2006
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W137
Overview
The W137 was developed to meet the Intel(R) Mobile Clock specification for the BX chipset, including Super I/O and USB support. The W40S11-02 is the Intel-defined companion part used for driving 2 SDRAM DIMM modules. Please see that data sheet for additional information. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. The -0.5% modulation profile matches that defined as acceptable in Intel's clock specification. Upon W137 power-up, the first 2 ms of operation are used for input logic selection. During this period the output buffers are tri-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or logic LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next, the output buffers are enabled, which converts both l/O pins into operating clock outputs. The 2-ms timer is started when VDD reaches 2.0V. The input latches can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock output is <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Functional Description
I/O Pin Operation Pins 14, 26, and 27 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connection.
Figure 1. Input Logic Selection Through Resistor Load Option
Figure 2. Input Logic Selection Through Jumper Option
Rev 1.0, November 24, 2006
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W137
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% of the selected frequency. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated through I/O pin #26.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Figure 4. Typical Modulation Profile
Rev 1.0, November 24, 2006
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W137
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.)
Unit V C C C kV
DC Electrical Characteristics:
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%; CPU0:1 = 66.6/100 MHz Parameter Supply Current IDD3PD IDD3 IDD2 IDD2PD VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL 3.3V Supply Current in Power-down mode 3.3V Supply Current 2.5V Supply Current 2.5V Supply Current in Power-down mode Input Low Voltage Input High Voltage Input Low Input High Current[2] Current[2] PWR_DWN# = 0 Outputs Loaded[1] Outputs Loaded[1] PWR_DWN# = 0 GND - 0.3 2.0 1 80 30 0.2 A 5 100 45 1 0.8 VDD + 0.3 -25 10 -5 +5 IOL = 1 mA PCI_F, PCI1:5, REF0:1 CPU0:1 CPU0:1 PCI_F, PCI1:5 REF0:1 IOH Output High Current CPU0:1 PCI_F, PCI1:5 REF0:1 Crystal Oscillator VTH CLOAD CIN,X1 X1 Input Threshold Voltage[3] Load Capacitance, As Seen by External Crystal X1 Input Capacitance[5]
[4]
Description
Test Condition
Min.
Typ.
Max.
Unit mA mA mA mA V V A A A A mV V V
Logic Inputs
Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current:
Clock Outputs 50 3.1 2.2 80 70 50 80 70 50 120 110 70 120 110 70 1.65 14 Pin X2 unconnected 28 180 140 90 180 140 90 IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.5V VDDQ3 = 3.3V
mA mA mA mA mA mA V pF pF
Notes: 1. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 2. CPU_STOP#, PCI_STOP#, PWR_DWN#, SPREAD#, and SEL48# logic inputs have internal pull-up resistors (not CMOS level). 3. X1 input threshold voltage (typical) is VDD/2.
Rev 1.0, November 24, 2006
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W137
DC Electrical Characteristics: (continued)
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%; CPU0:1 = 66.6/100 MHz Parameter Pin Capacitance/Inductance CIN COUT LIN Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Except X1 and X2 5 6 7 pF pF nH Description Test Condition Min. Typ. Max. Unit
AC Electrical Characteristics
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Min. Typ. Max. 15 5.2 5.0 1 1 45 4 4 55 200 15.5 CPU = 100 MHz Min. 10 3.0 2.8 1 1 45 4 4 55 200 Typ. Max. Unit 10.5 ns ns ns V/ns V/ns % ps
Output Rise Edge Rate Measured from 0.4V to 2.0V Output Fall Edge Rate Measured from 2.0V to 0.4V Duty Cycle Jitter, Cycle-to-Cycle Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V
tSK fST
Output Skew
175 3
175 3
ps ms
Frequency StabiliAssumes full supply voltage reached zation from Power-up within 1 ms from power-up. Short cycles (cold start) exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 13.5
Zo
13.5
Notes: 4. The W137 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Rev 1.0, November 24, 2006
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W137
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF) CPU = 66.6/100 MHz Parameter
tP tH tL tR tF tD tJC tSK tO fST Zo
Description
Period High Time Low Time
Test Condition/Comments
Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V
Min.
30 12.0 12.0 1 1 45
Typ.
Max.
Unit
ns ns ns
Output Rise Edge Rate Measured from 0.4V to 2.4V Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V
4 4 55 250 500
V/ns V/ns % ps ps ns ms
CPU to PCI Clock Offset Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Frequency Stabilization Assumes full supply voltage reached within 1 ms from from Power-up (cold power-up. Short cycles exist prior to frequency stabilistart) zation. AC Output Impedance Average value during switching transition. Used for determining series termination value.
1.5
4.0 3
20
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter
f tR tF tD fST Zo
Description
Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle
Test Condition/Comments
Determined by crystal oscillator frequency Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V
Min.
14.318 0.5 0.5 45
Max.
Typ.
2 2 55 3
Unit
MHz V/ns V/ns % ms
Frequency Stabilization from Assumes full supply voltage reached within 1 ms Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 25
48 MHz and 24 MHz Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter
f fD m/n tR tF tD fST Zo
Description
Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle
Test Condition/Comments
Determined by PLL divider ratio (see n/m below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V
Min.
Typ.
48.008 24.004 +167
Max.
Unit
MHz ppm
57/17, 57/34 0.5 0.5 45 2 2 55 3 V/ns V/ns % ms
Frequency Stabilization from Assumes full supply voltage reached within 1 ms Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 25
Rev 1.0, November 24, 2006
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W137
Ordering Information
Part Number W137H W137HT Lead-Free CYW137OXC CYW137OXCT 28-pin SSOP 28-pin SSOP -Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70C 28-pin SSOP 28-pin SSOP -Tape and Reel Type Production Flow Commercial, 0 to 70C Commercial, 0 to 70C
Package Diagrams
28-Lead (5.3 mm) Shrunk Small Outline Package O28
14 1.14 1 1.14 DIA. PIN 1 ID.
1.14 7.50 8.10
DIMENSIONS IN MILLIMETERS MIN. MAX.
15 10.00 10.40
28
SEATING PLANE 0.65 BSC.
.235 MIN. GAUGE PLANE 2.00 MAX. 1.65 1.85 0.05 0.21 0.25
0 MIN.
0.10
0.22 0.38
5.00 5.60 1.25 REF. 0.55 0.95
0-8
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 24, 2006
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